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Integrated Circuit Systems, Inc.
ICS950208
Programmable Timing Control HubTM for P4TM
Recommended Application: CK-408 clock with driven mode only for Brookdale chipset with P4 processor. Output Features: * 3 - Pairs of differential CPU clocks @ 3.3V * 4 - 3V66 @ 3.3V * 10 - PCI @ 3.3V * 1 - 48MHz @ 3.3V fixed * 1 - 24_48MHz selectable output @ 3.3V * 2 - REF @ 3.3V, 14.318MHz Features/Benefits: * Programmable output frequency. * Programmable output divider ratios. * Programmable output rise/fall time. * Programmable output skew. * Programmable spread percentage for EMI control. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Supports I2C Index read/write and block read/write operations. * Uses external 14.318MHz crystal. Key Specifications: * CPU Output Jitter <150ps * 3V66 Output Jitter <250ps * CPU Output Skew <100ps
Pin Configuration
*MULTSEL1/REF1 1 VDDREF 2 X1 3 X2 4 GND 5 *FS2/PCICLK_F0 6 *FS3/PCICLK_F1 7 PCICLK_F2 8 VDDPCI 9 PCICLK1 11 PCICLK2 12 GND 13 PCICLK3 14 PCICLK4 15 PCICLK5 16 PCICLK6 17 VDDPCI 18 Vttpwr_GD# 19 RESET# 20 GND 21 *FS0/48MHz 22 *FS1/24_48MHz 23 AVDD48 24 *FS4/PCICLK0 10 48 REF0/MULTSEL0* 47 GNDREF 46 VDDCPU 45 CPUCLKT2 44 CPUCLKC2 43 GNDCPU 42 PD# 41 CPUCLKT0 40 CPUCLKC0 39 VDDCPU 38 CPUCLKT1 37 CPUCLKC1 36 GNDCPU 35 IREF 34 AVDD 33 GND 32 VDD3V66 31 3V66_0 30 3V66_1 29 GND 28 3V66_2 27 3V66_3 26 SCLK 25 SDATA
48-SSOP
* Internal Pull-Up Resistor of 120K to VDD
Frequency Table
Bit2 FS4 0 0 0 0 0 0 0 0 0 Bit7 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit6 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit5 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit4 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 102.00 105.00 108.00 111.00 114.00 117.00 120.00 123.00 126.00 130.00 136.00 140.00 144.00 148.00 152.00 156.00 160.00 164.00 166.60 170.00 175.00 180.00 185.00 190.00 66.80 100.20 133.60 200.40 66.60 100.00 200.00 133.33 3V66 MHz 68.00 70.00 72.00 74.00 76.00 78.00 80.00 82.00 72.00 74.30 68.00 70.00 72.00 74.00 76.00 78.00 80.00 82.00 66.60 68.00 70.00 72.00 74.00 76.00 66.80 66.80 66.80 66.80 66.60 66.60 66.60 66.60 PCI MHz 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 36.00 37.10 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 33.30 34.00 35.00 36.00 37.00 38.00 33.40 33.40 33.40 33.40 33.30 33.30 33.30 33.30
Block Diagram
PLL2 /2 48MHz 24_48MHz REF (1:0)
0 0 0 0 0 0 0 1 1 1
X1 X2
XTAL XTAL OSC
PLL1 Spread Spectrum Spectrum Control Logic
CPU DIVDER
3 3
CPUCLKT (2:0) CPUCLKC (2:0) PCI PCICLK (6:0), PCICLK_F (1:0) 3V66 (3:0) RESET# I REF
1 1 1
PCI DIVDER
10
1 1
PD# MULTSEL(1:0) MULTSEL(1:0) FS (4:0) SDATA SD SCLK Vtt_PWRGD#
3V66 DIVDER
1 1 1 1 1 1 1 1
4
Config. Reg.
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ICS950208
Integrated Circuit Systems, Inc.
ICS950208
General Description
The ICS950208 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR memory. It provides all necessary clock signals for such a system. The ICS950208 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With all these programmable features ICS's, TCH makes mother board testing, tuning and improvement very simple.
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME *MULTSEL1/REF1 VDDREF X1 X2 GND *FS2/PCICLK_F0 *FS3/PCICLK_F1 PCICLK_F2 VDDPCI *FS4/PCICLK0 PCICLK1 PCICLK2 GND PCICLK3 PCICLK4 PCICLK5 PCICLK6 VDDPCI Vttpwr_GD# RESET# GND *FS0/48MHz *FS1/24_48MHz AVDD48 PIN TYPE I/O PWR IN OUT PWR I/O I/O OUT PWR #N/A OUT OUT PWR OUT OUT OUT OUT PWR IN OUT PWR I/O I/O PWR DESCRIPTION 3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference clock. Ref, XTAL power supply, nominal 3.3V Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Frequency select latch input pin / 3.3V PCI free running clock output. Frequency select latch input pin / 3.3V PCI free running clock output. Free running PCI clock not affected by PCI_STOP# . Power supply for PCI clocks, nominal 3.3V #N/A PCI clock output. PCI clock output. Ground pin. PCI clock output. PCI clock output. PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input. Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. Ground pin. Frequency select latch input pin / Fixed 48MHz clock output. 3.3V Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V. Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 2X drive
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ICS950208
Pin Description (Continued)
PIN PIN # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME SDATA SCLK 3V66_3 3V66_2 GND 3V66_1 3V66_0 VDD3V66 GND AVDD IREF GNDCPU CPUCLKC1 CPUCLKT1 VDDCPU CPUCLKC0 CPUCLKT0 PD# GNDCPU CPUCLKC2 CPUCLKT2 VDDCPU GNDREF REF0/MULTSEL0* PIN TYPE I/O IN OUT OUT PWR OUT OUT PWR PWR PWR OUT PWR OUT OUT PWR OUT OUT IN PWR OUT OUT PWR PWR I/O DESCRIPTION Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Ground pin. 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Power pin for the 3V66 clocks. Ground pin. 3.3V Analog Power pin for Core PLL This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the CPU outputs "Complimentary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal "Complimentary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 1.8ms. Ground pin for the CPU outputs "Complimentary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Ground pin for the REF outputs. 3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference clock.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 2X drive
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ICS950208
Maximum Allowed Current
Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND 40mA 360mA
Condition Powerdown Mode (PWRDWN# = 0) Full Active
CPUCLK Swing Select Functions
MULTSEL0 0 0 0 0 1 1 1 1 MULTSEL1 0 0 1 1 0 0 1 1 Board Target Trace/Term Z 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms Reference R, Iref= Vdd/(3*Rr) Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Output Current Ioh = 5*Iref Ioh = 5*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 7*Iref Ioh = 7*Iref Voh @ Z, Iref=2.32mA 0.71V @ 60 0.59V @ 50 0.85V /2 60 0.71V @ 50 0.56V @ 60 0.47V @ 50 0.99V @ 60 0.82V @ 50
0 0 0 0 1 1 1 1
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0 0 1 1 0 0 1 1
30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv)
Ioh = 5*Iref Ioh = 5*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 7*Iref Ioh = 7*Iref
0.75V @ 30 0.62V @ 20 0.90V @ 30 0.75V @ 20 0.60 @ 20 0.5V @ 20 1.05V @ 30 0.84V @ 20
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ICS950208
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
*See notes on the following page.
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ICS950208
Byte 0: Functionality and frequency select register (Default=0)
Bit Bit2 Bit7 Bit6 Bit5 Bit4 CPUCLK MHz
Description 3V66 MHz PCICLK MHz Spread % +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread 0 to -0.5% Down spread 0 to -0.5% Down spread 0 to -0.5% Down spread 0 to -0.5% Down spread
PWD
FS4 FS3 FS2 FS1 FS0
Bit (2,7:4)
Bit 3 Bit 1 Bit 0
0 0 0 0 0 102.00 68.00 34.00 0 0 0 0 1 105.00 70.00 35.00 0 0 0 1 0 108.00 72.00 36.00 0 0 0 1 1 111.00 74.00 37.00 0 0 1 0 0 114.00 76.00 38.00 0 0 1 0 1 117.00 78.00 39.00 0 0 1 1 0 120.00 80.00 40.00 0 0 1 1 1 123.00 82.00 41.00 0 1 0 0 0 126.00 72.00 36.00 0 1 0 0 1 130.00 74.30 37.10 0 1 0 1 0 136.00 68.00 34.00 0 1 0 1 1 140.00 70.00 35.00 0 1 1 0 0 144.00 72.00 36.00 0 1 1 0 1 148.00 74.00 37.00 0 1 1 1 0 152.00 76.00 38.00 0 1 1 1 1 156.00 78.00 39.00 1 0 0 0 0 160.00 80.00 40.00 1 0 0 0 1 164.00 82.00 41.00 1 0 0 1 0 166.60 66.60 33.30 1 0 0 1 1 170.00 68.00 34.00 1 0 1 0 0 175.00 70.00 35.00 1 0 1 0 1 180.00 72.00 36.00 1 0 1 1 0 185.00 74.00 37.00 1 0 1 1 1 190.00 76.00 38.00 1 1 0 0 0 66.80 66.80 33.40 1 1 0 0 1 100.20 66.80 33.40 1 1 0 1 0 133.60 66.80 33.40 1 1 0 1 1 200.40 66.80 33.40 1 1 1 0 0 66.60 66.60 33.30 1 1 1 0 1 100.00 66.60 33.30 1 1 1 1 0 200.00 66.60 33.30 1 1 1 1 1 133.33 66.60 33.30 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit 2,7:4 0 - Normal 1 - Spread spectrum enable 0 - Watch dog safe frequency will be selected by latch inputs 1 - Watch dog safe frequency will be programmed by Byte 10 bit (4:0)
Note 1
0 0 0
Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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ICS950208
Byte 1: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 45,44 38,37 41,40 PWD 1 1 1 X X X X X Description CPUT/C2 CPUT/C1 CPUT/C0 FS4 Read FS3 Read FS2 Read FS1 Read FS0 Read
b a ck b a ck b a ck b a ck b a ck
Byte 2: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 17 16 15 14 12 11 10 PWD 1 1 1 1 1 1 1 1 Description Reserved PCICLK_6 PCICLK_5 PCICLK_4 PCICLK_3 PCICLK_2 PCICLK_1 PCICLK_0
Byte 3: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Pin# 23 22 8 7 6
PWD 1 1 1 X 0 1 1 1
Description 24-48MHz 48MHz Reset gear shift detect 1 = Enable, 0 = Disable Reserved Sel 24_48; 0=24 MHz; 1=48 MHz PCICLK_F2 PCICLK_F1 PCICLK_F0
Byte 4: Output Control Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 31 30 48 1 27 28 PWD X X 1 1 1 1 1 1 Description MultiSEL0 (read back) MultiSEL1 (Read back) 3V66-0 3V66-1 REF0 REF1 3V 66_3 3V 66_2
Notes: 1. PWD = Power on Default 2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC off, and external resistor termination will bring CPUCLKC low.
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ICS950208
Byte 5: Programming Edge Rate (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# X X X X X X X X PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Byte 6: Vendor ID Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Revision ID Bit3 Revision ID Bit2 Revision ID Bit1 Revision ID Bit0 Vendor ID Bit3 Vendor ID Bit2 Vendor ID Bit1 Vendor ID Bit0
PWD X X X X 0 0 0 1
Description Revision ID values will be based on individual device's revision (Reserved) (Reserved) (Reserved) (Reserved)
Byte 7: Revision ID and Device ID Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Device ID7 Device ID6 Device ID5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID0
PWD Description 0 0 1 Device ID values will be based on individual device 0 "28H" in this case. 1 0 0 0
Byte 8: Byte Count Read Back Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0
PWD Description 0 0 0 Note: Writing to this register will configure byte count and how 0 many bytes will be read back, default is 0FH = 15 bytes. 1 1 1 1
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ICS950208
Byte 9: Watchdog Timer Count Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
PWD Description 0 0 0 The decimal representation of these 8 bits corresponds to X * 0 290ms the watchdog timer will wait before it goes to alarm mode and resets the frequency to the safe setting. Default at power up is 1 8 * 290ms = 2.3 seconds. 0 0 0
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Program Enable WD Enable WD Alarm S F4 S F3 S F2 S F1 S F0
PWD 0 0 0 0 1 0 0 0
Description Programming Enable bit 0 = no programming. Frequencies are selected by HW latches or Byte0 1 = enable all I2C programing. Watchdog Enable bit. This bit will over write WDEN latched value. 0 = disable, 1 = Enable. Watchdog Alarm Status 0 = normal 1= alarm status Watchdog safe frequency bits. Writing to these bits will configure the safe frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Ndiv 8 Mdiv 6 Mdiv 5 Mdiv 4 Mdiv 3 Mdiv 2 Mdiv 1 Mdiv 0
PWD X X X X X X X X
Description N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the reference divider value. Default at power up is equal to the latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Name Ndiv 7 Ndiv 6 Ndiv 5 Ndiv 4 Ndiv 3 Ndiv 2 Ndiv 1 Ndiv 0
PWD Description X X X The decimal representation of Ndiv (8:0) correspond to the X VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte 11. X X X X
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ICS950208
Byte 13: Spread Spectrum Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name SS 7 SS 6 SS 5 SS 4 SS 3 SS 2 SS 1 SS 0
PWD Description X X The Spread Spectrum (12:0) bit will program the spread X precentage. Spread precent needs to be calculated based on the X VCO frequency, spreading profile, spreading amount and spread X frequency. It is recommended to use ICS software for spread X programming. Default power on is latched FS divider. X X
Byte 14: Spread Spectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved Reserved Reserved SS 12 SS 11 SS 10 SS 9 SS 8
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit 12 Spread Spectrum Bit 11 Spread Spectrum Bit 10 Spread Spectrum Bit 9 Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name CPUDIV3 CPUDIV2 CPUDIV1 CPUDIV0 CPU Div 3 CPU Div 2 CPU Div 1 CPU Div 0
PWD X X X X X X X X
Description CPU2 clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. CPU(1:0) clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name 3V66 Div 3 3V66 Div 2 3V66 Div 1 3V66 Div 0 3V66 Div 3 3V66 Div 2 3V66 Div 1 3V66 Div 0
PWD X X X X X X X X
Description 3V66(3:2) clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. 3V66(1:0) clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
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ICS950208
Byte 17: Output Divider Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name 3V66(3:2)_INV 3V66(1:0)_INV CPU_INV CPU_INV PWD X X X X X X X X Description 3V66(3:2) Phase Inversion bit 3V66(1:0) Phase Inversion bit CPUCLK_2 Phase Inversion bit CPUCLK Phase Inversion bit
PCI Div 3 PCI Div 2 PCI Div 1 PCI Div 0
PCI clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 2. Default at power up is latched FS divider.
Table 1
Div (3:2) Div (1:0) 00 01 10 11 00 /2 /3 /5 /7 01 /4 /6 /10 /14 10 /8 /12 /20 /28 11 /16 /24 /40 /56
Table 2
Div (3:2) Div (1:0) 00 01 10 11 00 /4 /3 /5 /7 01 /8 /6 /10 /14 10 /16 /12 /20 /28 11 /32 /24 /40 /56
Byte 18: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name CPU_Skew 1 CPU_Skew 0 Reserved Reserved CPU_Skew 1 CPU_Skew 0 Reserved Reserved PWD 0 1 0 0 0 1 0 0 Description These 2 bits delay the CPUCLKC/T2 with respect to CPUCLKC/T (1:0) 00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps Reserved Reserved These 2 bits delay the CPUCLKC/T (1:0) clock with respect to CPUCLKC/T2 00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps Reserved Reserved
Byte 19: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name These 4bits control CPU-3V66(3:2)
PWD 0 1 0 0 0 1 0 0 0 0 1 1 1 1 0 1 0 1 1 1 0 0 0 0 0 1
Programming Sequence 0 0 0 0 1 0 0ps 150ps 300ps 450ps 600ps 750ps Reserved Reserved Reserved Reserved Reserved Reserved
These 4 bits control CPU-3V66(1:0)
1 1 1 1 900ps Reserved Reserved Reserved
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Byte 20: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name These 4bits control CPU-PCI(9:0)
PWD 1 0 0 0 1 0 0 0 0 0 1 1 1 1 0 1 0 1 1 1 0 0 0 0 0 1
Programming Sequence 0 0 0 0 1 0 0ps 150ps 300ps 450ps 600ps 750ps Reserved Reserved Reserved Reserved Reserved Reserved
Reserved
1 1 1 1 900ps Reserved Reserved Reserved
Byte 21: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name PCICLK_2_Slew 1 PCICLK_2_Slew 1 PCICLK_F (1:0)_Slew 0 PCICLK_F (1:0)_Slew 0 3V66 (3:2)_Slew 1 3V66 (3:2)_Slew 1 3V66 (1:0)_Slew 1 3V66 (1:0)_Slew 0
PWD 1 0 1 0 1 0 1 0
Description PCICLK2 clock slew rate control bits. 01 = strong:11 = normal; 10 = weak PCICLK_F(1:0) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak 3V66 (2:1) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak 3V66 (1:0) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak
Byte 22: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name REF Slew 1 REF Slew 0 PCI (6:4) Slew 1 PCI (6:4) Slew 0 PCI (3:2) Slew 1 PCI (3:2) Slew 0 PCI (1:0) Slew 1 PCI (1:0) Slew 0 PWD 1 0 1 0 1 0 1 0 Description REF clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI (6:4) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI (3:2) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI (1:0) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak
Byte 23: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Reserved Reserved Reserved Reserved 48MHz Slew 1 48MHz Slew 0 24_48MHz Slew 1 24_48MHz Slew 0
PWD Description X X Reserved 1 0 1 48MHz clock slew rate control bits. 01 = strong: 11 = normal; 10 = weakk 0 1 24_48MHz clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak 0
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ICS950208
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance Clk Stabilization Skew
1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD(op) IDDPD Fi CIN CINX TSTAB TSK3V66-PCI TCPUT-3V66
CONDITIONS
MIN 2 VSS - 0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 100MHz CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq. VT = 1.5V/VT = 1.5 V VT = 50% /VT = 1.5 V
MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA mA
203 23 11 27 1.5 1 2.5 5.58 14.31818
260 40 16 5 45 1.8 3.5
mA mA MHz pF pF ms ns
1
1
1
Guaranteed by design, not 100% tested in production.
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Integrated Circuit Systems, Inc.
ICS950208
Electrical Characteristics - CPUCLKT/C
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Current Source Output Zo Vo = Vx 3000 Impedance VR = 475 +1%; IREF = VOH Output High Voltage IOH Output High Current 2.32mA; IOH = 6*IREF 1 tr VOL = 0.175V, VOH = 0.525 V 175 Rise Time 1 tf VOH = 0.525 V, VOL = 0.175 V 175 Fall Time 1 dt VT = 50% 45 Duty Cycle Differential Crossover Vx Note 3 280 1 Voltage 1 tsk VT = 50% Skew VT = Vx Jitter, Cycle-to-cycle1 tjcyc-cyc
1
TYP
MAX
UNITS
1.08 -14.81 328 312 50 290 35 100 1.2 700 700 55 430 100 150 V mA ps ns % mV ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3V +/-5%; CL= 10- 30pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN F01 Output Frequency RDSN1 Output Impedance VO = VDD*(0.5) 12 VOH1 IOH = -1mA Output High Voltage 2.4 VOL1 IOL = -1mA Output Low Voltage VOH =1.0V IOH1 Output High Current VOH =3.135V -33 VOL = 1.95 V 30 IOL1 Output Low Current VOL = 0.4V VOL = 0.4V, VOH =2.4V Rise Time tr1 0.5 VOH = 2.4V, VOL = 0.4V 0.5 Fall Time tf1 VT = 1.5V Duty Cycle dt1 45 VT = 1.5V Skew tsk1 VT = 1.5V Jitter tjcyc-cyc
1
TYP 33.33
MAX 55 0.55 -33
UNITS MHz
V V mA mA ns ns % ps ps
1.94 1.78 51.9 133 225
38 2 2 55 500 250
Guaranteed by design,not 100% tested in production
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Integrated Circuit Systems, Inc.
ICS950208
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER SYMBOL 1 Output Frequency FO1 1 Output Impedance RDSP1 VOH1 Output High Voltage VOL1 Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
CONDITIONS VO = VDD*(0.5) IOH = -1mA IOL = -1mA VOH =1.0V VOH =3.135V VOL = 1.95 V VOL = 0.4V VOL = 0.4V, VOH =2.4V VOH = 2.4V, VOL = 0.4V VT = 1.5V VT = 1.5V VT = 1.5V
MIN 12 2.4
IOH1 IOL1 tr1 tf1 dt1 tf1 tjcyc-cyc1
-33 30 0.5 0.5 45 45
TYP MAX UNITS 66.66 MHz 55 V 0.55 V -33 mA mA ns ns % ps ps
1.94 1.78 50.7 82 245
38 2 2 55 500 250
Guaranteed by design,not 100% tested in production
Electrical Characteristics - 24, 48MHz
TA = 0 - 70C; VDD = 3.3V +/-5%; CL= 10-30pF (unlessotherwise stated) PARAMETER SYMBOL CONDITIONS 1 Output Frequency VO = VDD*(0.5) FO 1 Output Impedance VO = VDD*(0.5) RDSN1 VOH1 IOH = -1mA Output High Voltage VOL1 IOL = -1mA Output Low Voltage VOH =1.0V IOH1 Output High Current VOH =3.135V VOL = 1.95 V IOL1 Output Low Current VOL = 0.4V 1 VOL = 0.4V, VOH =2.4V Rise Time tr1 1 VOH = 2.4V, VOL = 0.4V Fall Time tf1 1 VT = 1.5V Duty Cycle dt1 1 VT = 1.5V Jitter tjcyc-cyc
1
MIN 12 2.4
TYP 24, 48
MAX 55 0.55 -29
UNITS MHz
V V mA mA ns ns % ps
-23 29 1 1 45 1.25 1.25 52 150 27 2 2 55 350
Guaranteed by design,not 100% tested in production
0464B--08/04/03
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Integrated Circuit Systems, Inc.
ICS950208
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL 1 FO1 1 RDSP1 VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tjcyc-cyc1
CONDITIONS VO = VDD*(0.5) IOH = -1mA IOL = -1mA VOH =1.0V VOH =3.135V VOL = 1.95 V VOL = 0.4V VOL = 0.4V, Voh =2.4V VOH = 2.4V, VOL = 0.4V VT = 1.5V VT = 1.5V
MIN 20 2.4
TYP 14.318
MAX 60 0.55 -33
UNITS MHz
V V mA mA
-33 30 0.5 0.5 45 1.71 1.68 54 450 38 2 2 55 500
ns ns % ps
Guaranteed by design,not 100% tested in production
0464B--08/04/03
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Integrated Circuit Systems, Inc.
ICS950208
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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Integrated Circuit Systems, Inc.
ICS950208
Un-Buffered Mode 3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci.
3V66 PCICLK_F and PCICLK Tpci
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Integrated Circuit Systems, Inc.
ICS950208
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950208yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device
0464B--08/04/03
19

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